- mult on off
- CAE/CRR and Epass
- KE, span and fraction
- quadrupoles
Changes needed to FPGA:
- remove DAC1 mode, not supported?
- Decimate should have a separate Delta T routine, 32 bits, call once per transfer cycle, no need to slice into 10 us intervals then sum back to 10 ms...
Changes to PC GUI
- Add gpib controls
- add noise calculation
- decimate by summation
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